1) Design Verification - IP/SOC, PCIe / Ethernet / USB , OVM/UVM - [ID 014]

• Experience in creating IP and Full Chip level verification plan and test-benches from scratch using Verilog/System Verilog/OVM/UVM/Specman.
• Experience in architecture and validation of CPUs, SOCs and industry standard IPs.
• Experience with development and usage of BFMs, transactors and protocol checkers used in simulation and HW emulation.
• Experience on Low Power designs, UPF based flows
• Experience with scripting in Perl/TCL/shell to automate flows.
• Knowledge in IP and SOC development flows and methodologies.
• Proficient in all aspects of pre-silicon validation (functional, DFT, power, coverage, gate level).
• Experience in delivering IPs or integrating IPs working with internal and external customers.
• Create validation plan using product/IP specifications/customer req